- cross-posted to:
- riscv@lemmy.ml
- cross-posted to:
- riscv@lemmy.ml
cross-posted from: https://lemmy.zip/post/35528933
China is doubling down on the RISC-V architecture.
cross-posted from: https://lemmy.zip/post/35528933
China is doubling down on the RISC-V architecture.
“reduced” is the super power. I would much rather put the smarts into the assembler/compiler/interpreter than the silicon. have been followed RISC since the 80’s and discovered that I am really a RISC guy living in CISC world. open arch is the world dominating cherry-on-top.
Do you have any resources by any chance that explain the difference well?
I work in high level software, so understand the benefit of doing things at ide time vs compile time vs runtime, and I’ve coded in assembly back in the day and understand instruction sets at a very rough level, but I’m not really familiar with specifically what differentiates RISC / ARM / x64, or why RISC’s reductions would be good / bad / what trade-offs come with them.
between the 30k’ overview of Reduced instruction set computer (RISC) architecture and the lower level RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA, you should get a pretty decent feel for it.
the level of optimization you get via hardware and software tooling is honestly pretty spectacular. I have been waiting for RISC to come out of hiding for years and it seems to be happening.