Can anyone explain the significance of this? I’m pretty technology-literate, but I am not seeing a big advantage of this over any other Linux machine? Genuinely curious.
RISC-V is a set of instructions implementable to processors that do not need licensing fees and controlling restrictions imposed. Due to its reduced instruction set; it uses less power in general but is harder to write compilers that work on it.
Having it more popularised opens up the doors for more enthausists to enter developing with it.
Harder to write compilers for RISC? I would argue that CISC is much harder to design a compiler for.
That being said there’s a lack of standardized vector/streaming instructions in out-of-the-box RISC-V that may hurt performance, but compiler design wise it’s much easier to write a functional compiler than for the nightmare that is x86.
The Vector extension has been ratified since 2021 it’s a standard part of the spec just don’t expect a random microcontroller to support it.
The SpacemiT K1 is 64GCVB and RVA22, doesn’t say which specific RVA22 there’s some without Vector support but it says in “GCVB” so w/e, also, “VLEN 256/128-bit x2 execution width”, if I’m parsing that correctly means you either get 256-bit vector registers or set the whole thing to 128 and then get (roughly) twice the ops/s.
And yes it’s much easier to emit vector code than to deal with the nightmare that’s SIMD. It’s as if Intel would’ve been sensible ages ago and not introduced SIMD but expanded on repnz stosb to make it useful for things other than memcpy. And no Intel has no excuse: Crays existed when they decided on SIMD.
How good are the RISC-V vector instructions implementations IRL? I’ve never heard of them. My experience with ARM is that even on certain data center chips the performance gains are abyssal (when using highly optimized libraries such as dpdk)
It’s bound to differ wildly. Most ARM chips are Contex Asomethings, that is, ARM designs, and those that aren’t are designed by companies with lots of resources… but also with mobile and embedded as their primary market so it’s not the primary focus. Most RISC-V cores are open source designs and/or created by startups, generally also not targeting HPC. The EU is investing into RISC-V HPC for EuroHPC (that is, supercomputers), you might be able to buy a chip associated with that soonish and try for yourself.
Heck, you can build a microcontroller-class chip that supports vector instructions – you just have to iterate element by element. Instruction support does imply that the instructions work, not that they’re fast.
That should be more on the BLAS side of things though, if you want to packet route I guess wait until Mikrotik ships boards with RISC-V SoCs, I haven’t heard anything and definitely not official statements but they’re bound to get on the train. They used Tilera in the past and as far as I’m aware the reason they switched away was Tilera overall failing, not because it didn’t work for the application. A structurally similar RISC-V chip should be quite easy to design and as it’s a standard architecture you don’t have to write your own libraries so it’s way easier to not go bankrupt doing it. Oh and Tilera of course definitely isn’t a Vector chip, it’s a “have a gazillion cores on a die, each barely larger than a DSP” kind of approach. You can have a core per pair of ports or whatever it is they’re doing.
Another interesting thing would be RISC-V GPUs. They do a lot of memory stuff that makes them so much better at BLAS stuff and vector instructions fit right into that. For proper graphics support you’d still need a custom ISA extension to wire up some odds and ends (say the texture units with their crazy indexing operations) but it’s definitely an option… which is unlikely to see HPC scale any time soon as I don’t see NVidia, AMD or Intel giving up the architectures they have.
One of the implications is the development and popularization of the RISC-V architecture, which is open and can open the market for more competition and less monopolies, among other things.
RISC-V is an open source chip design. As of today, it’s still worse than x86 (a CISC—“complex instruction set” design) and ARM (a proprietary RISC—“reduced instruction set” design) but if history is any indication, open source will end up overtaking them in the same way that, for instance, 98% of supercomputers today run highly customized versions of Linux.
There’s also some political connotations surrounding it because some countries don’t want high-end chip designs to be available to their perceived competitors (whether for protectionism reasons or military reasons) but it doesn’t matter.
Linux, being open, can already run on RISC-V while Windows ARM laptops are only really coming out now. Not sure if they have plans for RISC-V. Apple has long used ARM in phones and now their M chip laptops. Reduced instruction sets tend to have better battery life and (originally) worse performance so were ideal for mobile but over time, Intel/AMD (desktops/laptops) and ARM (basically all mobile chips) have borrowed ideas from each other. So, Apple’s ARM chips can be powerful and Intel/AMD chips can be power efficient if that’s the goal.
So, the main advantage of RISC-V is that there’s no royalties or, in some cases, the baggage of aging designs that need backwards compatibility. RISC-I was originally designed as a teaching tool for universities that didn’t want to pay royalties for student toy models and wasn’t really a corporate thing. RISC-V is (the fifth version as the Roman numeral V implies), got good enough to be useful in the real world. And now there’s a consortium of companies funding it and hoping to one day not have pay royalties to make chips.
So, there’s a lot of momentum behind RISC-V. It could easily be the primary architecture someday or, if nothing else, reduce the royalty rates of the other architectures.
It is a Linux machine. Runs a Debian derivative, and it’s not like Windows or anything else that isn’t Linux/BSD can run on a RISC-V laptop.
This isn’t the first RISC-V laptop, but the significance of a RISC-V laptop existing is primarily for developers who work on software targeting RISC-V systems. The ability to run RV64 programs without emulation and to natively compile RV64 software without cross-compilers is valuable to some people. Also, China in particular sees value in having computing products that aren’t affected by sanctions; the processor in this is designed and manufactured by a Chinese company without licensing any intellectual property from US or UK.
Explaining what RISC-V is
RISC-V is a relatively newer CPU instruction set architecture that competes with x86 (Intel, AMD) and ARM (Qualcomm, Ampere, MediaTek, etc.). Its current designs don’t really match those two in general-purpose performance yet but has the distinction of being a free, open, and extendable standard. Whereas x86 has only two CPU vendors and ARM has many vendors who all need to pay per-core license fees to ARM Holdings and have limits imposed on what they can do to it, RISC-V processors can be made by any hardware vendor with the means to make a processor and can be custom-designed to better fit specialized use-cases. Its use in general-purpose CPUs is catching on fastest in China but it sees use across the world in academia and in special-purpose processors by companies like Western Digital.
RISC and CISC are two language which your CPU speaks, and which have different strengths and weaknesses. Reduced Instruction Set Computer vs. Complex Instruction Set Computer. It’s something like Chinese vs. English. Either have a word for everything but that means there is a lot of words to learn, or have a smaller amount of words but that means you need more words to describe what you mean.
Highly technical; both been around for a while, and iirc usually CPUs use CISC, but RISC always retained it’s strengths, so scientists are always looking into the difference in application for both.
Ngl I have no clue why this technology is so newsworthy rn but I know Western countries made a fuss about China activitely pushing the lesser used RISC architecture.
Ngl I have no clue why this technology is so newsworthy rn
It’s because of openness/royalties.
RISC-V is an open standard instruction set architecture based on RISC principles. RISC itself is just a design type. ARM is based on RISC too, but it’s proprietary.
I assume you are familiar with what CPU architecture is. The famous one is x86 and ARM. This is just another one of those called RISC-V.
The significance is mostly political. US and allies have been trying to sanction China technologically. They even tried to block export of RISC-V, but since it is open source, they can just get fucked. Now, China can only get sub par GPU and limited CPU. Pushing for RISC-V means China is aiming to further develop it to be as capable as the CPU being sanctioned effectively making the sanction useless and even furthering Chinese manufacturing capabilities in the process.
The big advantage is that this is technically more standardized and free. Unlike ARM which require license, RISC-V doesn’t so anyone can make their own CPU and get the software support already in place. Hopefully more CPU manufacturers will be created from the advancement of RISC-V making more fierce competition.
Can anyone explain the significance of this? I’m pretty technology-literate, but I am not seeing a big advantage of this over any other Linux machine? Genuinely curious.
RISC-V is a set of instructions implementable to processors that do not need licensing fees and controlling restrictions imposed. Due to its reduced instruction set; it uses less power in general but is harder to write compilers that work on it.
Having it more popularised opens up the doors for more enthausists to enter developing with it.
Harder to write compilers for RISC? I would argue that CISC is much harder to design a compiler for.
That being said there’s a lack of standardized vector/streaming instructions in out-of-the-box RISC-V that may hurt performance, but compiler design wise it’s much easier to write a functional compiler than for the nightmare that is x86.
The Vector extension has been ratified since 2021 it’s a standard part of the spec just don’t expect a random microcontroller to support it.
The SpacemiT K1 is 64GCVB and RVA22, doesn’t say which specific RVA22 there’s some without Vector support but it says in “GCVB” so w/e, also, “VLEN 256/128-bit x2 execution width”, if I’m parsing that correctly means you either get 256-bit vector registers or set the whole thing to 128 and then get (roughly) twice the ops/s.
And yes it’s much easier to emit vector code than to deal with the nightmare that’s SIMD. It’s as if Intel would’ve been sensible ages ago and not introduced SIMD but expanded on
repnz stosbto make it useful for things other than memcpy. And no Intel has no excuse: Crays existed when they decided on SIMD.How good are the RISC-V vector instructions implementations IRL? I’ve never heard of them. My experience with ARM is that even on certain data center chips the performance gains are abyssal (when using highly optimized libraries such as dpdk)
It’s bound to differ wildly. Most ARM chips are Contex Asomethings, that is, ARM designs, and those that aren’t are designed by companies with lots of resources… but also with mobile and embedded as their primary market so it’s not the primary focus. Most RISC-V cores are open source designs and/or created by startups, generally also not targeting HPC. The EU is investing into RISC-V HPC for EuroHPC (that is, supercomputers), you might be able to buy a chip associated with that soonish and try for yourself.
Heck, you can build a microcontroller-class chip that supports vector instructions – you just have to iterate element by element. Instruction support does imply that the instructions work, not that they’re fast.
That should be more on the BLAS side of things though, if you want to packet route I guess wait until Mikrotik ships boards with RISC-V SoCs, I haven’t heard anything and definitely not official statements but they’re bound to get on the train. They used Tilera in the past and as far as I’m aware the reason they switched away was Tilera overall failing, not because it didn’t work for the application. A structurally similar RISC-V chip should be quite easy to design and as it’s a standard architecture you don’t have to write your own libraries so it’s way easier to not go bankrupt doing it. Oh and Tilera of course definitely isn’t a Vector chip, it’s a “have a gazillion cores on a die, each barely larger than a DSP” kind of approach. You can have a core per pair of ports or whatever it is they’re doing.
Another interesting thing would be RISC-V GPUs. They do a lot of memory stuff that makes them so much better at BLAS stuff and vector instructions fit right into that. For proper graphics support you’d still need a custom ISA extension to wire up some odds and ends (say the texture units with their crazy indexing operations) but it’s definitely an option… which is unlikely to see HPC scale any time soon as I don’t see NVidia, AMD or Intel giving up the architectures they have.
If that is true I don’t think it can be attributed to it being RISC
https://stackoverflow.com/questions/20298991/does-generally-risc-processors-have-lower-power-consumption-than-cisc-processors
This still runs Linux, or whatever else you want to run, it just has a RISC-V CPU instead of an x86 or ARM one
One of the implications is the development and popularization of the RISC-V architecture, which is open and can open the market for more competition and less monopolies, among other things.
RISC-V is an open source chip design. As of today, it’s still worse than x86 (a CISC—“complex instruction set” design) and ARM (a proprietary RISC—“reduced instruction set” design) but if history is any indication, open source will end up overtaking them in the same way that, for instance, 98% of supercomputers today run highly customized versions of Linux.
There’s also some political connotations surrounding it because some countries don’t want high-end chip designs to be available to their perceived competitors (whether for protectionism reasons or military reasons) but it doesn’t matter.
More info for anyone who wants it:
Linux, being open, can already run on RISC-V while Windows ARM laptops are only really coming out now. Not sure if they have plans for RISC-V. Apple has long used ARM in phones and now their M chip laptops. Reduced instruction sets tend to have better battery life and (originally) worse performance so were ideal for mobile but over time, Intel/AMD (desktops/laptops) and ARM (basically all mobile chips) have borrowed ideas from each other. So, Apple’s ARM chips can be powerful and Intel/AMD chips can be power efficient if that’s the goal.
So, the main advantage of RISC-V is that there’s no royalties or, in some cases, the baggage of aging designs that need backwards compatibility. RISC-I was originally designed as a teaching tool for universities that didn’t want to pay royalties for student toy models and wasn’t really a corporate thing. RISC-V is (the fifth version as the Roman numeral V implies), got good enough to be useful in the real world. And now there’s a consortium of companies funding it and hoping to one day not have pay royalties to make chips.
So, there’s a lot of momentum behind RISC-V. It could easily be the primary architecture someday or, if nothing else, reduce the royalty rates of the other architectures.
It is a Linux machine. Runs a Debian derivative, and it’s not like Windows or anything else that isn’t Linux/BSD can run on a RISC-V laptop.
This isn’t the first RISC-V laptop, but the significance of a RISC-V laptop existing is primarily for developers who work on software targeting RISC-V systems. The ability to run RV64 programs without emulation and to natively compile RV64 software without cross-compilers is valuable to some people. Also, China in particular sees value in having computing products that aren’t affected by sanctions; the processor in this is designed and manufactured by a Chinese company without licensing any intellectual property from US or UK.
Explaining what RISC-V is
RISC-V is a relatively newer CPU instruction set architecture that competes with x86 (Intel, AMD) and ARM (Qualcomm, Ampere, MediaTek, etc.). Its current designs don’t really match those two in general-purpose performance yet but has the distinction of being a free, open, and extendable standard. Whereas x86 has only two CPU vendors and ARM has many vendors who all need to pay per-core license fees to ARM Holdings and have limits imposed on what they can do to it, RISC-V processors can be made by any hardware vendor with the means to make a processor and can be custom-designed to better fit specialized use-cases. Its use in general-purpose CPUs is catching on fastest in China but it sees use across the world in academia and in special-purpose processors by companies like Western Digital.
RISC-V is a CPU architecture, like x86 or ARM. You can run Linux on it.
RISC and CISC are two language which your CPU speaks, and which have different strengths and weaknesses. Reduced Instruction Set Computer vs. Complex Instruction Set Computer. It’s something like Chinese vs. English. Either have a word for everything but that means there is a lot of words to learn, or have a smaller amount of words but that means you need more words to describe what you mean.
Highly technical; both been around for a while, and iirc usually CPUs use CISC, but RISC always retained it’s strengths, so scientists are always looking into the difference in application for both.
Ngl I have no clue why this technology is so newsworthy rn but I know Western countries made a fuss about China activitely pushing the lesser used RISC architecture.
It’s because of openness/royalties.
RISC-V is an open standard instruction set architecture based on RISC principles. RISC itself is just a design type. ARM is based on RISC too, but it’s proprietary.
ARM even means “Advanced RISC Machines”. They changed the official name to ARM but I don’t think they actually reinterpreted it.
I assume you are familiar with what CPU architecture is. The famous one is x86 and ARM. This is just another one of those called RISC-V.
The significance is mostly political. US and allies have been trying to sanction China technologically. They even tried to block export of RISC-V, but since it is open source, they can just get fucked. Now, China can only get sub par GPU and limited CPU. Pushing for RISC-V means China is aiming to further develop it to be as capable as the CPU being sanctioned effectively making the sanction useless and even furthering Chinese manufacturing capabilities in the process.
The big advantage is that this is technically more standardized and free. Unlike ARM which require license, RISC-V doesn’t so anyone can make their own CPU and get the software support already in place. Hopefully more CPU manufacturers will be created from the advancement of RISC-V making more fierce competition.
This will give you a basic understanding. Sorry for the YouTube link. It’s from the channel called Explaining Computers.
https://youtu.be/Ps0JFsyX2fU
Here is an alternative Piped link(s):
https://piped.video/Ps0JFsyX2fU
Piped is a privacy-respecting open-source alternative frontend to YouTube.
I’m open-source; check me out at GitHub.
Good bot.
This IS a Linux machine. Do you know what a CPU architecture is?