- cross-posted to:
- technology@lemmy.ml
- cross-posted to:
- technology@lemmy.ml
You must log in or register to comment.
Eh. LPCAMM seems more useful overall as a product. Faster DDR at this point in time has diminishing returns.
It’ll be interesting to see how this plays out though, because there are a few different paths to solve this type of problem with DDR5. Personally, I’d love for much lower power, but a wider bus, which is where I thought things were heading.
Well we’ve seen CAS latency increase almost quicker than DDR speeds. CAMM should address this issue by shortening the distance from cpu to RAM, at least for laptops.
I’d say DIMM has pretty much stranded in DDR5.
faster ram generally has dimishing returns on sustem use, however it does matter for gpu compute reasons on igpu (e. g gaming, and ML/AI would make use of the increased memory bandwith).
its not easily to simply just push a wider bus because memory bus size more or less affects design complexity, thus cost. its cheaper to push memory clocks than design a die with a wider bus.
Computational-Fluid-Dynamics simulations are RAM-limited, iirc.
I’m presuming many AI models are, too, since some of them require stupendous amounts of RAM, which no non-server machine would have.
“diminishing returns” is what Intel’s “beloved” Celeron garbage was pushing.
When I ran Memtest86+ ( or the other version, don’t remember ), & saw how insanely slow RAM was, compared with L2 or L3 cache, & then discovered how incredible the machine-upgrade going from SATA to NVMe was…
Get the fastest NVMe & RAM you can: it puts your CPU where it should have been, all along, and that difference between a “normal” build vs an effective build is the misframing the whole industry has been establishing, for decades.
_ /\ _
Well usually yes, but if cpu manufacturers decide to really lean into cramming lots of cores into cpu-s (Like Intel’s big.LITTLE cpus, but even more cores), then we probably will need faster RAM-s, since more core == more memory bandwith demand, and currently this issue has been always resolved by faster RAMs. (Or we could just increase the memory channels)
Standardized by JEDEC earlier this year as JESD323, CUDIMMs tweak the traditional unbuffered DIMM by adding a clock driver (CKD) to the DIMM itself, with the tiny IC responsible for regenerating the clock signal driving the actual memory chips. By generating a clean clock locally on the DIMM (rather than directly using the clock from the CPU, as is the case today), CUDIMMs are designed to offer improved stability and reliability at high memory speeds, combating the electrical issues that would otherwise cause reliability issues at faster memory speeds. In other words, adding a clock driver is the key to keeping DDR5 operating reliably at high clockspeeds.
